============================================================== Guild: wafer.space Community Channel: ℹ️ - Information / general / featherlane-PEX After: 2026-06-30 11:59 p.m. Before: 2026-08-01 12:00 a.m. ============================================================== [2026-07-12 12:57 a.m.] namibj the big one is up to "Extracting VSS" now. [2026-07-12 1:25 a.m.] namibj yeah so that's definitely not the linear solver I want to use with that behavior.... _I think ?_ {Attachments} 2026-07_media/Xyce_log_2026-07-12T00_33_4400_00-2D05C.cat [2026-07-12 1:25 a.m.] namibj {Attachments} 2026-07_media/tb_fl_mcpu32.xyce-25C34.prn [2026-07-12 1:41 a.m.] namibj @Tholin results [2026-07-12 1:42 a.m.] namibj If you have amendments to this file, now's the time, to get results before sleepy time. {Attachments} 2026-07_media/tb_fl_mcpu32_currents_v2-17849.xyce [2026-07-12 1:54 a.m.] namibj on second thought, I'm gonna take the scarce hours of cold to sleep sooner than later, not gonna be that long anyways, and afterwards the big circuit should maybe be done. [2026-07-12 1:54 a.m.] namibj (done extracting, that is) [2026-07-12 5:19 p.m.] namibj @Tholin errrrr, this got 87 mA? {Attachments} 2026-07_media/tb_fl_mcpu32_currents_v2.xyce-4A72A.prn [2026-07-12 5:20 p.m.] tholin Oh [2026-07-12 5:20 p.m.] tholin I wonder if its because the latches have initialized into a metastable state [2026-07-12 5:21 p.m.] tholin 87 mA doesn’t feel like a short [2026-07-12 5:22 p.m.] tholin I wish I could simulate a few clock cycles [2026-07-12 5:22 p.m.] tholin The best thing I can suggest for a DC analysis is pulling clk_n high [2026-07-12 5:24 p.m.] namibj it should be solving until they stabilize; I'm running with the other solver from earlier again to check though. [2026-07-12 5:24 p.m.] namibj Feel free to compare the voltages between the two `.prn` files to see if they may be meaningfully different. [2026-07-12 5:28 p.m.] namibj Feel free to edit this into a smol testbench for that; think about `MINTIMESTEPSBP` and the tolerance tunables please to dial in a minimum of actually to-be-taken timesteps that would still be expected to give meaningful results. A full nonlin solve there didn't take _thaaaat_ long: ``` ***** Solution Summary ***** Number Successful Steps Taken: 1 Number Failed Steps Attempted: 0 Number Jacobians Evaluated: 362 Number Linear Solves: 362 Number Failed Linear Solves: 0 Number Linear Solver Iterations: 70583 Number Residual Evaluations: 373 Number Nonlinear Convergence Failures: 0 Total Residual Load Time: 78.2002 seconds Total Jacobian Load Time: 61.0558 seconds Total Linear Solution Time: 1952.14 seconds ***** Total Simulation Solvers Run Time: 2152.39 seconds ***** Total Elapsed Run Time: 2247.1 seconds ***** ``` {Attachments} 2026-07_media/tb_fl_mcpu32_currents_v3.2-2A9A5.xyce [2026-07-12 5:31 p.m.] tholin I’m not sure if there are any syntax differences with xyce [2026-07-12 5:34 p.m.] tholin But, in theory, all you need to do is update the beginning of the input stimulus section to ``` *** 5. INPUT STIMULUS *** V_clk clk VSS PULSE( 0 3.3 0 0.1ns 0.1ns 50ns 200ns ) V_clk_n clk_n VSS PULSE( 0 3.3 100ns 0.1ns 0.1ns 50ns 200ns ) V_rst_n rst_n VSS PULSE( 0 3.3 375ns 0.1ns 0.1ns 5us 6us ) V_rst_override_n rst_override_n VSS PULSE( 0 3.3 375ns 0.1ns 0.1ns 5us 6us ) ``` And then run that for a few clock cycles and observe the outputs. This is set up for a 5us long run. [2026-07-12 5:35 p.m.] tholin I tried this in ngspice and it just never even started [2026-07-12 6:00 p.m.] namibj feel free to check; notably btw. I've thought you _might_ want to use `.option timeint ERROPTION=1` to explicitly **not** use the classic SPICE "local truncation error", but instead just adjust step size based on how many newton (or whatever nonlinear solver was selected) iterations it took to turn the predictor's (the trapezoidal/backwards-euler/2nd-order-gear time integration forward-model) estimate of the solution variable's values (e.g. node voltages and a bunch of (internal) port currents) into a new solution that is newly compliant with all the non-linear device interaction models up to the configured tolerances (absolute, relative, and what the scale reference is for "relative"; sadly AFAIK there's no straight-forward way to distinguish between current and voltage quantities for that config option, which would be IMO fairly relevant for abstol as e.g. tolerance better than like a single millivolt is probably not required for this type of circuit if one wants to check against DOA and isn't trying to do fancy calibration stuff; also not to forget update-norm and unweighted l2-norm of the residual which are also tunables for deeming the nonlinear solve "sufficciently converged"). {Attachments} 2026-07_media/Xyce_UG_2-87380.pdf 2026-07_media/Xyce_RG_1-1002B.pdf [2026-07-12 6:07 p.m.] namibj I can mint you a rawfile that you can use with the xschem-integrated viewer. I'd suggest you take a single standard cell from your library, let me run it through the PEX extractor script, and let me hand you a starter-pack Xyce testbench for it (half machine-generated per your wishes as to the excitation pattern for it, but then substantially manually checked by me for not being broken and actually tested), if you want. Also, if you can generate me a `.gds` flattened as much as this and with no stray labels littered around, you are then allowed to _have labels on internal nets of interest_ or I'd guess there would be some way from the LVS machinery to slap semantically meaningful labels on nets and/or devices. I'll see to get a `.nodeset`-based initial conditions dump next run which should make it much faster to jump in and test things. {Attachments} 2026-07_media/fl_mcpu32_flattened_only_m4_labels-2D116.gds [2026-07-12 8:04 p.m.] tholin Hold on, I’m trying again with ngspice {Attachments} 2026-07_media/image-23F6F.png [2026-07-12 8:04 p.m.] tholin I flattened the layout in magic before extracting it, maybe that helps [2026-07-12 8:24 p.m.] tholin It did it! [2026-07-12 8:24 p.m.] tholin And oh man am I happy I tested this because there is a breaking bug in the RTL that I see now [2026-07-12 8:50 p.m.] tholin I also see the 87mA static current consumption. Not sure what’s up with that. [2026-07-12 9:26 p.m.] tholin I ran a simulation on a LibreLane generated layout. Less standard cells in it, but still had a ~9mA static current consumption. [2026-07-12 9:26 p.m.] tholin Possible that its an issue with my SCL? Or the 3.3V FETs have that much of a leakage current? [2026-07-12 9:27 p.m.] tholin Because it roughly scales up to the 87mA consumption by standard cell count [2026-07-12 9:48 p.m.] tholin Cursed spice deck just containing 3000 buff_16s with the input tied low seems to suggest leakage [2026-07-12 9:52 p.m.] tholin Whoa! what the hell? It freaks the hell out if I instantiate 4000 fillcap cells! {Attachments} 2026-07_media/image-5BFE2.png [2026-07-12 9:52 p.m.] tholin I guess its the inrush? [2026-07-12 9:52 p.m.] tholin It crashed, btw [2026-07-12 9:53 p.m.] tholin It was supposed to run for much longer [2026-07-12 9:54 p.m.] tholin I also noticed that well tap cells extract into.... nothing. Like, empty spice file. So, what exactly is energizing the wells during these simulations, then? [2026-07-12 10:16 p.m.] tholin I don’t think I have the time to figure out why the static current consumption on my SCL is so high [2026-07-12 10:16 p.m.] tholin I’m just going to have to tape out and pray [2026-07-12 10:26 p.m.] namibj > . The P(*) and W(*) wildcards are supported for analysis > modes (TRAN and DC) that support power calculations. YAY [2026-07-12 10:47 p.m.] tholin Not sure how to approach this. If it is one specific cell that is at fault, it might be somewhat difficult to find. [2026-07-12 10:47 p.m.] namibj I'm back on the settings that did the fast results. [2026-07-12 10:48 p.m.] tholin I’m going to leave my computer running overnight to see if I can get a analysis done on a extract with parasitics [2026-07-12 10:48 p.m.] namibj Going by earlier processing speed, we should have info in about 30~40 minutes which extracted device(s) are to blame for the power dissipation. [2026-07-12 10:48 p.m.] namibj I'm not doing transient here btw. [2026-07-12 10:49 p.m.] namibj Can you share the testbench spice? [2026-07-12 10:50 p.m.] namibj And/or that for this mentioned smaller/"more minimized" SCL-bug-reproducer? [2026-07-12 10:52 p.m.] tholin I just extracted with `extract all;ext2sim labels on;ext2sim;extresist tolerance 10;extresist;ext2spice lvs;ext2spice cthresh 0;ext2spice extresist on;ext2spice;` [2026-07-12 10:53 p.m.] tholin This seems to pull 7.5mA static {Attachments} 2026-07_media/secret_message-E9EAA.gds [2026-07-12 10:56 p.m.] tholin Inputs low [2026-07-12 11:17 p.m.] namibj Here ya go! {Attachments} 2026-07_media/tb_fl_mcpu32_currents_v4.xyce-8C1B3.ic 2026-07_media/tb_fl_mcpu32_currents_v4.xyce-D39CC.powers https://media.githubusercontent.com/media/wafer-space/discord.wafer.space/master/large_media/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/featherlane-pex/2026-07/2026-07_media/tb_fl_mcpu32_currents_v4.xyce.ascii-C0232.raw 2026-07_media/tb_fl_mcpu32_currents_v4.xyce-29E72.prn 2026-07_media/tb_fl_mcpu32_currents_v4-5722C.xyce [2026-07-12 11:20 p.m.] tholin I decided to be funny and re-run the flow of secret_message with all logic cells disabled in my SCL except NAND and NOT [2026-07-12 11:20 p.m.] tholin And that made it WORSE [2026-07-12 11:20 p.m.] tholin 7.5mA static to 12mA static [2026-07-12 11:20 p.m.] tholin Corresponding roughly to the increase in the number of transistors [2026-07-12 11:20 p.m.] tholin This feels like leakage [2026-07-12 11:21 p.m.] namibj I mean, I guess? [2026-07-12 11:22 p.m.] namibj And if that's the case, this sounds like runaway self-heating waiting to happen. [2026-07-12 11:22 p.m.] tholin As I said, I’m going to have to just tape out and hope [2026-07-12 11:23 p.m.] namibj re-running with the other possibly-easier-to-digest print formats active for the power print line [2026-07-12 11:23 p.m.] namibj (using the initial conditions file created) [2026-07-13 12:55 a.m.] tholin I did an extraction with resistors and it now idles at 1.9mA instead of 12mA [2026-07-13 1:03 a.m.] namibj "with resistors"? as opposed to including capacitors, or what? [2026-07-13 1:04 a.m.] namibj {Attachments} 2026-07_media/tb_fl_mcpu32_currents_v4.1.xyce-0CA99.ic 2026-07_media/tb_fl_mcpu32_currents_v4.xyce.powers-8DED5.tecplot 2026-07_media/tb_fl_mcpu32_currents_v4.xyce.powers-9F661.probe 2026-07_media/tb_fl_mcpu32_currents_v4.1.xyce-58D16.prn https://media.githubusercontent.com/media/wafer-space/discord.wafer.space/master/large_media/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/featherlane-pex/2026-07/2026-07_media/tb_fl_mcpu32_currents_v4.xyce.ascii-F9368.raw 2026-07_media/tb_fl_mcpu32_currents_v4.xyce.powers-ED43D.csv [2026-07-13 1:04 a.m.] namibj one of the "powers" should be fairly easy to wrangle into a comfy table [2026-07-13 1:05 a.m.] tholin Oh, I’ve been doing only transistors so far [2026-07-13 1:07 a.m.] namibj oh, I've been doing full PEX [2026-07-13 1:07 a.m.] namibj ``` ***** Device Count Summary ... C level 1 (Capacitor) 280984 D level 1,2 (Diode) 9694 M level 14 (BSIM4) 44848 R level 1 (Resistor) 267528 V level 1 (Independent Voltage Source) 22 --------------------------------------------- Total Devices 603076 ***** Setting up matrix structure... ***** Number of Unknowns = 292543 ***** Initializing... Analyzed Singleton Problem: --------------------------- Singletons Detected! Num Singletons: 44 --------------------------- ConstructedSingleton Problem: --------------------------- RatioOfDimensions: 0.99985 RatioOfNonzeros: 0.765899 --------------------------- ZOLTAN Load balancing method = 10 (HYPERGRAPH) ***** Solution Summary ***** Number Successful Steps Taken: 1 Number Failed Steps Attempted: 0 Number Jacobians Evaluated: 558 Number Linear Solves: 558 Number Failed Linear Solves: 0 Number Linear Solver Iterations: 69386 Number Residual Evaluations: 571 Number Nonlinear Convergence Failures: 0 Total Residual Load Time: 103.587 seconds Total Jacobian Load Time: 104.901 seconds Total Linear Solution Time: 2080.07 seconds ***** Total Simulation Solvers Run Time: 2370.69 seconds ***** Total Elapsed Run Time: 2547.76 seconds ***** ***** End of Xyce(TM) Simulation ***** ``` [2026-07-13 1:08 a.m.] namibj (turns out, loading from `.nodeset`'s doesn't make it faster; it takes almost twice as long instead... maybe only +50% time) ============================================================== Exported 67 message(s) ==============================================================